Feedback sample-and-hold circuit transversal filter banks which rely upon MOS transistors to perform the function of the sampling switches present a problem with respect to both fixed pattern noise and power supply noise.
The fixed pattern noise arises from the characteristics of the MOS transistor switching devices. In each sample-and-hold stage, a holding capacitor is connected to the signal through an MOS sampling switch which is responsive to a switching pulse train from a switching control source. When the switch is operated from its conductive "on" condition to its resistive "off" condition by the pulse train to make the change from signal tracking to signal hold, there occurs a switching charge feedthrough error which affects the voltage on the holding capacitor and therefore introduces in the held signal what is generally referred to as a "feedthrough voltage offset". Small variations among the MOS switching transistors in a given circuit lead to a variation in the respective feedthrough voltage offsets among the stages of the bank and result in a fixed pattern noise in its output signal.
The power supply rejection problem relates to a buffer through which the output signal from the holding capacitor must be taken in order to provide d.c. (direct current) isolation of the holding capacitor from any circuitry connected to the output of the bank. The holding capacitor is connected to the gate of an MOS buffer transistor, usually a source follower. The drain of the buffer transistor is coupled to a power voltage rail. With this arrangement, the gate-to-drain capacitance of the buffer transistor provides a parasitic coupling of power supply noise to the holding capacitor.